Dual Path PLLs

This is a short tutorial on dual path PLLs derived mostly from research papers published in IEEE, my experience in designing them. It will start with a very brief re-capitulation of the ‘classic’ PLLs and then reason out the necessity of dual loop PLLs.

Re-capitulation of the ‘classic’ charge pump PLL

Classic charge pump PLL [1]

The figure above shows the classical charge pump PLL. Note that Kvco is the gain of the VCO in Hz/V [and thus the 2*pi factor].

Assuming that the reader is well conversant with the phase domain model, I will directly jump into the equations:

The filter transfer function is given by \text{K}_{\text{LF}}(\text{s}) = \frac{\text{s}\tau _\text{1} +\text{1}}{\text{s}(\text{s}\tau _\text{2} + \text{1})(\text{C}_\text{1}+\text{C}_\text{2})} where \tau _1 = R_1C_1
and
\tau _2=\tau _1 \frac{C_2}{C_1+C_2}
The closed loop transfer function is given by H(s)=\frac{(s\tau _1 +1)K_{VCO}I_{CP}}{s^2(s\tau _2 +1)(C_1+C_2)}

There are two poles at origin, which means that the initial slope of the magnitude curve will be -40dB/decade. Then there is a zero (F_1 ) and another pole (F_2 ) . For stability reasons, the zero must come before the UGB to slow down the roll off rate to a -20dB/decade slope. [So that at UGB you would have gained some phase from the -180 degrees at DC]. The pole due to \tau _2 must come after the zero to ensure the non-zero phase margin. This can be seen from the figure below:

Bode plot of third order PLL [1]

For the sake of completeness, F_1=\frac{1}{2\pi R_1C_1} and F_2 \approx \frac{1}{2\pi R_1C_2}

The UGB is approximately given by \frac{I_{CP}K_{VCO}R}{2\pi N} . Note that this expression is only true if F_2 is far from the UGB.

Before we plunge into the dual loop PLL, lets talk about a few more points [The reason will become apparent shortly].

What happens when we increase the gain of the VCO? Increasing the gain of the VCO will only move the magnitude curve up. This means that the UGB point moves to the right. However the phase curve does not change at all as the zero and the poles are determined only by the passive components. (see figure below)

This figure shows the magnitude and phase response of a typical charge pump PLL. The upper curves correspond to magnitude response, whereas the below ones correspond to phase

Normally, you would want the top of the bell to coincide with the UGB point. That ensures you have the best phase margin corresponding to the given values of R, C_1 and C_2 . [You can tune I_{CP} or the gain of the VCO to achieve that].

What is the maximum limit on the value of the UGB? The UGB of a charge pump PLL cannot be arbitrarily high. Gardener had shown in his paper on charge pump PLL that UGB should not be more than 1/7th the reference frequency on which PFD works. Much later Hanumolu showed that the limit is 1/3.4. As a rule of thumb, designers like to keep it at 1/8th to 1/7th. However, if the PLL is being used to filter out noise in the reference clock itself, the bandwidth will be made small. But that comes at a heavy penalty in the area of the loop filter.

Thus, to ensure that the UGB is not too high, designers go for:

  • Make sure that the VCO gain is not too high.
  • If the above is not possible, designers try to reduce the I_{CP} value to get back to a lower value of UGB.

The value of I_{CP} cannot be made arbitrarily small either. CP non-idealities will cause large reference spur, something that is abhorred.

The other option is to lower the value of R. The problem with this is that the zero moves to the right (close to the UGB; ideally the UGB should be far away from the zero to get close to 90 degrees of phase margin, and correspondingly the pole due to C_{2} must be far far right to the UGB) and can degrade the phase margin. To compensate for that, the C_{1} capacitor in the loop filter is increased by the same amount to get back the same position of zero.

Increasing capacitance increases the area of the PLL, something which is not appreciated.

There are a lot of places where we need a wide range of operating frequencies for the PLL. For example, lets say you are making a PLL to support frequency range for 2.5GHz to 5GHz. Assume that the gain of the PLL is 1GHz/V, and the VCO starts at 2.5GHz every time. Then the control voltage of the VCO needs to move around by at least 2.5V. The max voltage supported in the modern-day processes is 2.5V/1.8V/1.2V. TSMC’s T40LP [40nm] process supports voltage of 3.3V. It’s clearly not practical. And this ‘2.5V’ range does not even include the PVT variations on the center frequency of the VCO at startup, which would be 2-2.5X.

So, how about increasing the gain of the VCO? As described above, the loop filter area goes up.

There are multiple ways to get rid of these limitations.

Improving PLL range without degrading loop filter area

There are two ways to get around the above limitation.

  • Use a digital tuning method to bring the VCO’s initial frequency to close to what is the intended frequency of operation.
  • Use a ‘split tuned architecture
Different methods for PLL tuning [2]

The second technique shown alongside is the digital way. A calibration engine runs at the PLL startup which brings the PLL close to its desired range of operation. Once its close enough, the analog loop is allowed to close. The analog loop is completely unaware of the digital tuning. The gain of the VCO which the analog sees can be made small without compromising on the lock range on the PLL.

How small? Well, because this calibration happens only at startup and the temperature (and supply voltage) can change during operation. The charge pump by design can only support a finite value of control voltage change. This allowable output voltage compliance of the charge pump must cover the entire range of frequency change that can happen due to voltage and temperature variation. Using the above two values, the KVCO of the VCO required can be determined.

The third technique, which is the more interesting technique is what is called a dual loop PLL. It was first proposed in [1].

Split tuned PLLs

A VCO’s equation can be written as: f_{vco}=f_{center} + K_{VCO}v_{ctrl} . The secondary loop can be imagined to be tuning the f_center. Note that the output of the PFD contains information about both phase and frequency offset. Any frequency difference at the input of the PFD means that the average CP output will ramp up or down. The C1 node will just be a filtered replica of the CP output.

Split tuned PLL

Initially lets assume that F_vco exactly equals N*f_ref. Because the output v_c is from an integrator, and since the frequency is constant, then V_cap must be equal to V_ref. [Well only if the PLL is stable, and let us assume it is so]. Then the V_ctrl on an average must be equal to V_ref.

 Now lets say that the frequency output of the VCO has decreased to a value less than N*f_ref. [This can happen due to temperature variation on the VCO]. Then the average output of the CP will keep going up. The voltage of the C1 node will also exhibit the same trend. Because this voltage now becomes more than V_ref, the integrator starts integrating the difference. This increases the value of Vc, which in turn increases the frequency. If the integrator has a very low gain [AKA the loop is slow], then the moment f_vco becomes slightly more than N*f_ref, the V_ctrl and thus V_cap must come down, thus bringing it closer to V_ref. The loop eventually settles.

Note that, V_ctrl on average will become EQUAL to V_ref. [well, not exactly because the integrator will have some input referred offset, but the idea is that V_ctrl will be very close to V_ref]. This greatly simplifies the charge pump design.

Note that the tradeoffs on the gain of the VCO and the maximum allowable swing on the output of the charge pump goes away. But wait a minute. Which means that V_c will have to move a lot or the gain in that path must be high enough to accommodate the frequency range that we were able to do using digital calibration. Yes, absolutely. The differential OTAs used to make the integrator have a near rail to rail range, and the VCO gain in that path can be made larger compared to the ‘fine’ path without much of a penalty. It will become clear as we proceed. But lets do some mathematics.

The transfer function between the voltage at the capacitor (V_{cap} ) and the current from the charge pump (I_{in} ) can be written as:
K_{LFC1}(s) = \frac{K_{LF}(s)}{1+s\tau _1} = \frac{1}{s(s\tau _2 +1)(C_1+C_2)}

The transfer function between V_c and V_{cap} is given by
K_{GMC}(s)=\frac{\frac{g_m}{g_{out}}}{1+s\frac{C_3}{g_{out}}} = \frac{\frac{g_m}{g_{out}}}{1+s\tau _3}

The combined transfer function including both the paths can be written as:

L(s) = \frac{I_{CP}}{2\pi N}\left[ K_{LF}(s)\frac{K_{VCOFINE}}{s} + K_{LFC1}(s)K_{GMC}(s)\frac{K_{VCOCOARSE}}{s}\right]

When the two components in the brackets in the above expression becomes equal, a zero is encountered.

L(s) = \frac{I_{CP}}{2\pi N(C_1+C_2)s^2(1+s\tau _2)} \left[ (s\tau _1 +1)K_{VCOFINE} + \frac{\frac{g_m}{g_{out}}K_{VCOCOARSE}}{1+s\tau _3}\right]

Note that the system now has four poles and two zeros. Note that what we really intended was to reduce gain of the VCO without compromising on the locking range. To do that, the part corresponding to coarse path must become negligible before you encounter the first zero of the fine path. This is a roundabout way of saying that the zero due to the addition of the secondary path must be BEFORE the zero in the fine loop.

Bode plot of fourth order PLL [1]

Here F_3 corresponds to the pole of the integrator. [A real integrator behaves as an integrator only beyond the pole formed by the output impedance of the transconductor and the capacitance at the o/p node].

F_4 corresponds to the zero formed by the addition of the secondary loop.

\omega _4 = \frac{g_m}{C_3}\frac{K_{VCOCOARSE}}{K_{VCOFINE}}

Note that because F_4 needs to be at a low frequency, if the difference between the gains in the coarse and fine path are too large, then either C3 needs to be increased or gm needs to be increased. As already discussed, we don’t want to do that!

Before we proceed, lets do some quick calculations. Lets say the UGB is at 1MHz. Then the zero due to the fine loop needs to be at 200KHz (to have some good phase margin). The zero added due to secondary loop needs to be somewhere like 10-20KHz. Lets say the cap C3 is 20e-12 F. And if K_VCOCOARSE/K_VCOFINE were to be 5 [it can be large]. Then gm required would be in the order of 500nS! Its not trivial designing for such low values for transconductances.

Solution proposed in [2]

To reduce the value of gm, the paper proposed using duty cycling of the gm stage, whereby the gm stage will be turned on only for a very short period of time. This greatly reduces the value of effective transconductance! You can even go down to 1% duty cycling, and thus the area of the capacitor can be reduced to a very small value!

References

  1. S. Williams, H. Thompson, M. Hufford and E. Naviasky, “An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter,” Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), Orlando, FL, USA, 2004, pp. 151-154.
  2. T. Wu, P. K. Hanumolu, K. Mayaram and U. Moon, “A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop,” 2007 IEEE Custom Integrated Circuits Conference, San Jose, CA, 2007, pp. 547-550.